In integrated circuit design, verification tools are used to automatically check chip design structures. These tools need to analyze design structure by, e.g., clock domain crossing verification or low power structural verification. In such an analysis a tool searches for predetermined design patterns. When a pattern is found, characteristic parameters are determined. For example, input and output clock of logic blocks can be determined and analyzed. If the tool detects a mismatch in input and/or output an error is generated and presented to a user.
Design structures with the same technical functionality can be implemented in several different ways using different structures. Verification tools match specific structural patterns, rather than functionality. When the predetermined pattern is verified, a user can manually waive errors generated by that predetermined pattern. Variations of an approved predetermined pattern are not detected as also verified by the tool, because they do not structurally match the predetermined pattern. Therefore, the variations cause the verification tool to report the same or similar errors because they do not match the predetermined pattern. These errors also have to be waived by a user manually. This error waiving can be very time intensive when several thousand errors have to be reviewed and waived.